The desire for making ever smaller integrated circuits (IC's) has brought about the development and use of different lithographic approaches to accurately generate the IC components at nanometer scales. A particular approach used for semiconductor manufacturing is what is referred to as self-aligned multiple patterning (SAMP).
SAMP, while using nanometer wavelength lithography (e.g., 193 nm), is a primary lithography candidate for the generation of metal wire/interconnect layers associated with small (e.g., 10 nm, 7 nm and below) semiconductor manufacturing roadmaps. A particular implementation of SAMP used for the printing/generation of metal routing layers, is an implementation referred to as the “sidewall-is-dielectric” (SID) implementation.
This implementation of SAMP involves the printing of a set of lines utilizing what is referred to as a “mandrel” mask. The set of lines are lithographically printed at a relaxed pitch that will reliably print and yield in nanometer lithography (e.g., Deep Ultraviolet (DUV) lithography). Material is then grown onto the sidewall of those lines and the original relaxed-pitch “mandrel” lines are then removed, leaving only the sidewall lines. This, in effect, doubles the number of lines compared to the original pattern, and is often referred to as “self-aligned double patterning” (SADP).
Implementations of SAMP may also utilize a “trim” mask that is used to determine the metal patterns to be filled with metal during a metal fill process associated with the SAMP (e.g., a metal fill step and/or chemical mechanical polishing/planarization [CMP]). For example, the trim mask may be used for the creation of line ends for the metal pattern (i.e., areas where no metal is laid, indicating ends of metal lines).
Different approaches for the trim mask are available in SAMP. One approach is referred to as a “line-staggered” SAMP approach in which the trim mask has a trim pattern that correspond to areas of an etched inter-layer dielectric (ILD) that are not to be filled with metal (e.g., a metal layer of a technology process). The trim pattern of the trim mask for the line-staggered approach may be complex in that the trim pattern may have large or numerous shapes and/or may include multiple “turns” or corners within the pattern. Such complexity of the trim mask may facilitate “rounding” or misalignment errors which may result in yield issues for the trim mask and may translate to yield issues in the trimmed metal wires/fill.
A preferred approach is referred to as a “line-cut” SAMP approach in which the trim mask has a trim pattern that corresponds to areas of an etched ILD that are filled with metal that is either “active” metal or “redundant” metal (i.e., “dummy” metal). The trim pattern of the trim mask for the line-cut approach may be less complex in that the trim pattern may have simpler shapes with an avoidance of “turns” or corners within the trim pattern. Such reduced complexity may result in higher yielding trim masks for the line-cut approach, which may translate to reduced costs in manufacturing and for the end consumer.
A known tradeoff of this reduced complexity associated with the line-cut SAMP approach is a resulting parasitic capacitance penalty. For example, the additional metal lines, in the form of redundant metal, associated with the line-cut SAMP approach may result in increased parasitic capacitance between active metal lines and neighboring redundant metal lines. This increased parasitic capacitance may significantly reduce a circuit design's maximum achieved frequency. Additionally, the increased parasitic capacitance may in some cases result in as much as a 10% to 15% performance loss for circuit designs.
Furthermore, the line-cut SAMP approach may also be susceptible to the lithography limitations that are associated with other SAMP techniques. Limitations such as merging effects (e.g., in which shapes of a trim mask merge to form an erroneous trim pattern) or various misalignments associated with the trim mask may be encountered with the line-cut SAMP approach. The above described problems associated with SAMP implementations may result in reduced mask yields, increased cost, and diminished performance for IC designs in small (e.g., 10 nm, 7 nm and below) process technologies. A need exists to reduce or eliminate the above described problems associated with SAMP implementations.